1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing technologies and more particularly to GAA (Gate-All-Around) CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) devices.
2. Description of Related Art
A CMOS device integrates both NMOS (N-type Metal Oxide Semiconductor) and PMOS (P-type Metal Oxide Semiconductor) transistors in one device. As the device size continues to shrink, a major challenge in scaling down the channel length is to maintain a high current drive capability (Ion) and a good stable threshold voltage, and control the device leakage current (Ioff) within requirement. The short-channel effect degrades device performance and is a severe obstacle to scale down conventional planar CMOS devices.
For nanometer-scale channel length CMOS devices, it is important to control the channel conductance mainly through a gate electric field without being affected by a drain scattering electric field. For SOI devices, the above-described problem is alleviated with the reduced silicon thickness in both partial-depletion and full-depletion structures. Compared with the conventional planar CMOS devices, inversion mode dual-gate or tri-gate fin-type FETs have better gate control and scaling down capabilities. Besides operating in an inversion mode, ultra-thin SOI devices can operate in an accumulation mode. Comparing to the full-depletion FET, in an accumulation mode, current flows through the whole SOI device, which increases the carrier mobility, reduces low-frequency noises, lowers the short channel effect, and increases the threshold voltage so as to avoid polysilicon gate depletion effect. In an inversion mode FET, the type of impurities doped in the source and drain regions is different from that in the channel region, the conductive carriers are of minority carriers, and p-n junctions are formed between the source region and the channel region and between the drain region and the channel region, respectively. The inversion mode FETs are currently the most widely used devices. On the other hand, in an accumulation mode FET, the source and drain regions are doped with impurities of the same type as that in the channel region, the conductive carriers is of majority carriers, and there is no p-n junction. Since the carrier mobility is the bulk material mobility, the accumulation mode FET achieves high carrier mobility.
Further, in Si(110) substrates, current flows along <110>crystal orientation, hole mobility is more than doubled compared with in conventional Si(100) substrates, and electron mobility is the highest in Si(100) substrates. To fully utilize the advantage of the carrier mobility depending on crystalline orientation, M. Yang et al. at IBM developed a CMOS fabricating technology on hybrid substrates with different crystal orientations (‘High performance CMOS fabricated on hybrid substrate with different crystal orientations’, Digest of Technical Paper of International Electron Devices Meeting, 2003). Through bonding and selective epitaxy growth techniques, an NMOS device is fabricated on a Si (100) surface and a PMOS device is fabricated on a Si (110) surface. The paper reported the drive current of the PMOS device on the Si(110) substrate increases by 45%, when Ioff=100 nA/μm. But the PMOS device is fabricated on an epitaxy layer and does not have a buried oxide layer to isolate it from the substrate, thus adversely affecting the performance of the device performance.
Therefore, the present invention provides gate-all-around CMOSFET devices to overcome the above-described problems.